1. Field of the Invention
The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit in which current consumed by sense amplifiers is reduced, erroneous operation is prevented, and which can operate at high speed.
2. Description of the Related Art
In recent years, the storage capacity of semiconductor memory circuits (hereinafter also referred to as "memory") for use in microcomputers is increasing yearly.
An increase in the storage capacity of memories in high-speed microcomputers results in an increase in the load capacity on word lines and bit lines, leading to a reduction in the speed of operation. Therefore, it has been necessary to divide a memory into memory blocks for maintaining a desired speed of operation.
One conventional high-speed semiconductor memory circuit is shown in FIG. 1 of the accompanying drawings, and each of the memory blocks of the semiconductor memory circuit shown in FIG. 1 is shown in FIG. 2. FIG. 3 shows each of the sense amplifiers used in the memory blocks.
As shown in FIGS. 1 through 3, the conventional high-speed semiconductor memory circuit used in high-speed microcomputers comprises memory blocks 601, 602, tristate buffers 603, 604 for selecting outputs of the memory blocks 601, 602 with a most significant bit of address 611, and an inverter 605 for controlling the tristate buffer 604.
Each of the memory blocks 601, 602 comprises a decoder 712 for decoding an address 720 to select a word line 721, a plurality of memory cells 711 for making a corresponding bit line 722 active in response to the selection of the word line 721, an array of sense amplifiers 710 for amplifying signal changes in bit lines 722, a data latch 709 for latching output signals from the sense amplifiers 710 for the period in which a precharging signal PRI is PRI=0, a reference voltage generator 708 for generating a reference voltage RREF to be applied to the sense amplifiers 710, and an inverter 706.
Each of the sense amplifiers 710 comprises a plurality of nMOS transistors 807-811, a plurality of pMOS transistors 802-806, a NOR gate 801, and a pair of inverters 812, 813. In FIGS. 2 and 3, PRI represents a precharging signal, RD a sense amplifier de-energizing signal, S bit lines, RREF a reference signal, SOUT output signals from the sense amplifiers, and OUT an output signal from the memory block.
In the conventional memory, the two memory blocks 601, 602 shown in FIG. 1 are always operated, and one of the data outputs OUT0, OUT1 thereof is selected by the most significant bit of address 611. However, since the memory blocks are always in operation irrespective of whether they are selected or not, the conventional memory has suffered a problem in that the power consumption thereof increases as the number of memory blocks used increases. The memory blocks need to be in operation at all times in order to allow the memory to operate at high speed.
The power consumption of the memory may be reduced by de-energizing those memory blocks which are not selected by the most significant bit of address 611. If those memory blocks are de-energized, then the memory cannot operate at high speed. The reasons for the high-speed operation failure will be described below.
Prior to describing the overall operation of the memory, operation of each of the sense amplifiers 710 will be described below with reference to FIG. 4. In order to operate the sense amplifier 710, a predetermined reference voltage RREF generated by the reference voltage generator 708 is applied to the sense amplifier 710. Operation at the time the sense amplifier de-energizing signal RD is RD=0 will be described below.
During a precharging period 901, since the precharging signal PRI is PRI=1, the NOR gate 801 produces an output "0". The pMOS transistor 805 is turned on, increasing the potential of a line 814. At this time, if the bit line S is low in level, then the pMOS transistor 803 is turned on, turning on the nMOS transistor 809. Charges on the line 814 flow to charge the bit line S. When the voltage of the bit line S rises to a certain level, the nMOS transistor 808 starts being turned on, and the pMOS transistor 803 starts being turned off. Therefore, before the voltage of the bit line S reaches a power supply voltage, the nMOS transistor 809 is turned off, ending the precharging of the bit line S. Thus, the bit line S is precharged to a potential lower than the power supply voltage, which is determined by the ratio of the pMOS and nMOS transistors 803, 808 (see a precharged-voltage curve region indicated by 905 in FIG. 4).
The pMOS transistor 806 is turned off because the pMOS transistor 805 is turned on. Because the nMOS transistor 811 is turned on by the reference voltage RREF and the nMOS transistor 810 is turned on at all times, an input "0" is supplied to the inverter 812, so that the sense amplifier produces an output signal SOUT "0". During this period, an address is determined, and the decoder 712 selects one word line 721. The sense amplifier operates in the same manner during a precharging period 903.
Sampling periods 902, 904 will be described below. Since the precharging signal PRI is PRI=0 in these sampling periods 902, 904, the NOR gate 801 produces an output "1". Therefore, the pMOS transistor 805 is turned off. It is assumed that when a word line is selected as a result of the decoding of an address, the potential of a bit line drops in the period 902 and remains unchanged in the period 904.
In the period 902, the potential of the bit line drops. The pMOS transistor 803 starts being turned on, and the nMOS transistor 808 starts being turned off. Therefore, the nMOS transistor 809 starts being turned on, lowering the potential of the line 814. The pMOS transistor 806 then starts being turned on, and the potential of the input to the inverter 812 starts increasing, causing the sense amplifier to produce an output signal SOUT "1". Since the bit line has been precharged to a voltage lower than the power supply voltage, the bit line can be discharged at high speed, so that the sense amplifier can operate at high speed. In the period 904, inasmuch as the potential of the bit line remains unchanged, the potentials in various parts of the sense amplifier also remain unchanged. Thus, the sense amplifier produces the same output signal as the output signal produced in the period 903.
When the sense amplifier de-energizing signal RD is RD=1, the nMOS transistor 807 is turned on, the pMOS transistor 802 is turned off, and the NOR gate 801 produces an output "0". Consequently, the nMOS transistor 809 is turned off, and the pMOS transistor 805 is turned on. Irrespective of the precharging signal PRI, the line 814 is precharged, and the bit line S is disconnected by the nMOS transistor 809. Therefore, the sense amplifier always produces an output signal SOUT "0" because the nMOS transistor 811 is turned on by the reference voltage RREF and the nMOS transistor 810 is turned on at all times. This holds true in any period. As can be understood from the description so far, the sense amplifier is energized when the sense amplifier de-energizing signal RD is RD=0, and de-energized when the sense amplifier de-energizing signal RD is RD=1, disconnecting the bit line, with the result that the sense amplifier always produces an output signal SOUT "0".
For de-energizing the sense amplifier with the most significant bit of address in a conventional arrangement, a semiconductor memory circuit may be arranged as shown in FIG. 5 of the accompanying drawings, and a memory block may be arranged as shown in FIG. 6 of the accompanying drawings. Operation of this semiconductor memory circuit will be described below with reference to FIGS. 5, 6 and 7. FIG. 7 is a timing chart of an operation sequence for de-energizing the sense amplifier with the most significant bit of address. In FIG. 7, the solid-line curves represent waveforms of erroneous operation, and the dotted-line curves represent waveforms of ideal operation.
The memory block shown in FIG. 6 differs from the memory block shown in FIG. 2 in that a memory block selecting signal CS is applied via a NAND gate 1107, rather than the inverter 706, to produce a sense amplifier de-energizing signal RD for sense amplifiers 1110.
Since the switching of a reference voltage generator 1108 is time-consuming, a reference voltage ON signal REFON is turned on at all times.
Periods 1201-1204 in which the most significant bit of address is "0" in FIG. 7 will first be described below. The period 1201 is a precharged period, and the memory block selecting signal CS for a memory block 1002 is "1", selecting the memory block 1002. The NAND gate 1107 produces an output "0", and the sense amplifier de-energizing signal RD is "0". At this time, the sense amplifiers 1110 are precharged, and bit lines 1122 are precharged to a predetermined voltage lower than the power supply voltage.
On the other hand, the memory block selecting signal CS for a memory block 1001 is "0", not selecting the memory block 1001. Therefore, the NAND gate 1107 produces an output "1", and the sense amplifier de-energizing signal RD becomes "1", de-energizing the sense amplifiers 1110. At this time, the bit lines 1122 are disconnected from the sense amplifiers 1110. The bit lines 1122 thus disconnected may possibly be charged up due to other signals coupled thereto and extraneous noise.
In the period 1202, since the memory block selecting signal CS for the memory block 1002 is "1", the sense amplifiers 1110 are in a sampling state, and the bit lines 1122 are discharged. The sense amplifiers produce output signals SOUT "1", and the memory block produces an output OUT "1" immediately before the end of the period 1202. The memory block selecting signal CS for the memory block 1001 is "0", and the sense amplifiers 1110 thereof keep de-energized. At this time, as in the period 1201, the bit lines 1122 may possibly be charged up.
In the period 1203, the sense amplifiers 1110 are precharged as in the period 1201, and the output OUT0 of the memory block 1002 latches the sense amplifier outputs OUT in the period 1202 and produces "1". The memory block 1001 produces an output OUT1 "0".
In the period 1204, the sense amplifiers 1110 operate in substantially the same manner as in the period 1202. However, since the bit lines 1122 remain unchanged, the memory block produces an output OUT "0".
Periods 1205-1208 in which the most significant bit of address is "1" in FIG. 7 will be described below. The period 1205 is a precharged period. The sense amplifier de-energizing signal RD for the memory block 1002 is RD=0, so that the sense amplifiers 1110 are precharged, disconnecting the bit lines 1122. At this time, as shown in FIG. 7, the bit lines 1122 may possibly be charged up. In the memory block 1001, the bit lines 1122 tend to be precharged, but will not be precharged furthermore because they have already been at a potential greater than the preset voltage.
In the period 1206, the memory block 1002 remains in the same state as in the period 1205. In the memory block 1001, the potential of the bit lines 1122 starts being lowered. However, since the bit lines 1122 have been charged up to a potential higher than the preset potential due to other signals coupled thereto and extraneous noise, it takes more time to discharge the bit lines 1122 than it would have if they were not charged. Thus, the sense amplifier output signal SOUT changes with a delay, allowing erroneous data "0" to be latched by a data latch 1109.
In the periods 1207, 1208, the sense amplifiers 1110 operate normally because the bit lines 1122 have been discharged. However, in periods 1209, 1210 immediately after the selection of a memory block has been changed, the sense amplifiers 1110 suffer the same erroneous operation as described above.
As described above, the conventional memory with the above arrangement for de-energizing the sense amplifier with the most significant bit of address has been disadvantageous in that the operation of the memory is slowed down upon switching between the memory blocks, tending to result in an erroneous operation. Therefore, it has not been possible to use the conventional memory as it is.
Japanese laid-open patent publication No. 117178/82 discloses a memory circuit divided into memory blocks associated with respective differential amplifiers, which are selectively activated to read data at a relatively high speed without being subject to noise. Japanese laid-open patent publication No. 106266/98 reveals a semiconductor memory device having bit lines which are not associated with a selector switch, but associated with respective sense amplifiers which are selectively enabled to select a bit line, so that the number of transistors is reduced, the area of the layout is reduced, and the operating speed is increased. Each of the bit lines described in these publications comprises two complementary bit lines. Memory circuits other than RAMs, e.g., ROMs and FLASH EEPROMs use single bit lines for reducing the area of the layout. Even if the bit lines disclosed in the above publications include single bit lines, the publications fail to show any means for solving the problem that the operation of the memory is slowed down upon switching between the memory blocks, tending to result in an erroneous operation.